The present invention relates to high voltage field-effect transistors. More specifically, the present invention relates to processes for fabricating high voltage field-effect transistor structures that include a high-voltage junction field-effect transistor.
It is conventional to construct a high-voltage, insulated-gate, field-effect transistor (HVFET) having a high breakdown voltage and a low xe2x80x9con-statexe2x80x9d resistance. To accomplish this end, practitioners in the art have used an insulated gate field-effect transistor (IGFET) placed in series with a high-voltage junction field-effect transistor (JFET). Such a transistor is capable of switching at high voltages, has low values of on-state resistance, and has insulated-gate control. Moreover, the HVFET may advantageously be fabricated near low voltage logic transistors on a single integrated circuit chip to form what is commonly referred to as a power integrated circuit (PIC).
Lateral HVFETs with a JFET conduction channel have been used in power conversion applications such as in AC/DC converters for offline power supplies. One goal in such devices is to produce a transistor having a high breakdown voltage (Vbd) using as small a surface area as possible. In order to achieve high breakdown voltage in these devices is necessary to accurately control the amount of charge in the JFET conduction channel(s) and also in each of the JFET gate layers. For this reason, it is desirable to fabricate such devices using a process that minimizes variance in the charge of each layer.
It is also desirable to fabricate HVFETs that occupy as small a surface area as possible to realize a given on-state resistance. The figure of merit often used is known as specific on-resistance (Rsp), which is the product of on-state resistance and surface area. A lower Rsp allows a smaller area HVFET transistor to be used to meet the on-state resistance requirements of a given application, which reduces the area and, respectively, the cost of the PIC. One way of reducing the on resistance of a HVFET is to incorporate multiple JFET conduction channels into the transistor device.
Another goal in the art is to provide a highly manufacturable HVFET design that consistently delivers the required combination of Vbd and Rsp over a range of normal process variances. To realize this goal, the manufacturing process should introduce minimal variance in the critical device parameters, and the HVFET should exhibit minimal sensitivity to process variations.
To try to achieve the aforementioned goals, researchers and engineers have experimented with a variety of different structures and processing methods. For example, U.S. Pat. Nos. 5,146,298 and 5,313,082 both describe a method of fabricating an HVFET with multiple JFET conduction channels. The ""082 patent teaches a HVFET in which two JFET channels are arranged in parallel to increase charge and reduce Rsp. A triple diffusion process is disclosed, in which three separate implant and diffusion steps are required to form a HVFET (see FIG. 1 of the ""082 patent) that includes N-type top layer 28, P-layer 27, and N-type extended drain region 26. The multiple layers of alternating conductivity types is fabricated by implanting, and then diffusing, dopants into the semiconductor substrate. That is, according to the ""082 patent, the N-well region, the P-type buried region, and the N-type extended drain region are all diffused from the surface.
One shortcoming of this prior art approach is that each successive layer is required to have a surface concentration that is higher than the preceding layer, in order to fully compensate and change the conductivity type of the corresponding region. Diffusion of dopants from the surface makes it very difficult to maintain adequate charge balance among the layers. In addition, the heavily doped p-n junction between the buried layer and drain diffusion region degrades the Vbd of the device. The concentrations also tend to degrade the mobility of free carriers in each layer, thereby compromising the on-resistance of the HVFET. As a result of these difficulties, this method of manufacture is generally limited to producing HVFET devices having no more than two JFET conduction channels.
Another method of fabricating an HVFET with multiple JFET conduction channels is disclosed in U.S. Pat. No. 4,754,310. The ""310 patent teaches a method of construction that consists of epitaxially depositing material of alternating conductivity types and then forming V-shaped grooves to contact the resulting plurality of layers. This method suffers, however, from the high costs associated with multiple epitaxial deposition processing steps and the formation of the grooves. Furthermore, it is difficult to precisely control the charge in each layer formed by epitaxially deposition. As noted previously, proper charge control is crucial to achieving a device that is characterized by a consistently high breakdown voltage.
A similar method of fabricating an HVFET with multiple JFET conduction channels is described in an article by Fujihira entitled, xe2x80x9cTheory of Semiconductor Superjunction Devices,xe2x80x9d Jpn. J. Appl. Phys., Vol. 36, pp. 6254-6262 (October 1997). Fujihira also teaches the technique of epitaxial growth and the formation of grooves to fabricate the HVFET. This method suffers from the same charge control problems and high manufacturing cost discussed above.
Yet another method of fabricating an HVFET with multiple JFET conduction channels is disclosed in U.S. patent application Ser. No. 09/245,029, filed Feb. 5, 1999, of Rumennik, et. al., which application is assigned to the assignee of the present application. Rumennik teaches the use of multiple high-energy implants through the surface of the semiconductor substrate to form a plurality of buried layers. One drawback of this approach, however, is that the number and maximum depth of the buried layers is limited by the available implantation energy. For example, the maximum boron implantation energy available from a typical high-energy implanter is about 7 MeV. Using the techniques disclosed in Rumennik, such an implanter would allow for the formation of four separate buried layers, providing five JFET conduction channels, with a corresponding specific on-resistance of about 6 ohm-mm2.
By way of further background, U.S. Pat. No. 5,386,136 of Williams teaches a lightly doped drain (LDD) lateral MOSFET transistor having reduced peak electric fields at the gate edge. The peak electric field is reduced due to the presence of a P+ buried layer that pushes the electrical equipotential lines beneath the silicon surface laterally further and more evenly in the direction of the drain contact region. Yamanishi, et al. (JP404107877A) teaches construction of a P-buried layer in an extended drift region using processing technique of dopant segregation by thermal heating.
Thus, there still exists a need for a reliable, economically efficient method of fabricating HVFETs with multiple JFET conduction channels that overcomes the problems associated with the prior art.